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| 2004 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd16908 dc-dc converter ic for organic el displays data sheet document no. s17102ej2v0ds00 (2nd edition) date published october 2004 ns cp (k) printed in japan the mark shows ma j or revised p oints. description the pd16908 is composed of a 4ch step- up circuit (chopper method), a 2ch polarity-inverted circuit (chopper method) and a 3ch series regulator, and is ideal for the power supply for organic el displays. features ? output voltage setting function via serial interface ? on-chip soft start circuit ? low current consumption achieved by full cmos ? on-chip timer latch short-circuit protection circuit ? adjustable oscillation frequency (200 to 800 khz) ? mos fet directly driven by push-pull-confi gured output stage ? mounted on 56-pin plastic wqfn (8 x 8) ordering information part number package pd16908k9-5b4-a 56-pin plastic wqfn (8 x 8)
data sheet s17102ej2v0ds 2 pd16908 1. block diagram i i1 + ? ? ? + i i9 out9 out1 out2 pgnd1 fb1 lv dd test1 test2 agnd1 agnd2 v ref c dly c t r t c ss1 npv dd v dd 24 c ss2 28 c ss3 32 c ss4 37 c ss5 17 c ss6 21 39 38 41 40 9 10 8 34 11 53 52 43 shdnb 47 test3 48 n.c. 33 n.c. 29 n.c. 25 23 22 i i2 fb2 27 26 i i3 fb3 31 30 i i4 fb4 36 35 i i5 fb5 16 15 i i6 fb6 20 19 dcon 51 sda 45 scl 46 cs 44 50 49 18 42 pv dd 7 out3 pgnd2 5 pgnd4 3 6 out5 12 out6 14 out4 pgnd3 13 4 + ? ? ? + + ? ? ? + + ? ? ? + + ? ? ? + ? + + ? ? ? + i i8 out8 55 54 ? + i i7 out7 1 bv dd 2 56 ? + e/a1 pwm compa- rator 1 pwm compa- rator 2 pwm compa- rator 3 pwm compa- rator 4 pwm compa- rator 5 pwm comparator 6 e/a2 e/a3 e/a7 e/a8 e/a9 e/a4 e/a5 e/a6 control logic block and serial interface block soft start circuit triangular wave oscillator timer latch short-circuit protection circuit undervoltage lockout circuit reference voltage 2.0 v data sheet s17102ej2v0ds 3 pd16908 2. pin configuration (top view) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 out7 bv dd pgnd4 out4 pgnd2 out3 pv dd out2 pgnd1 out1 npv dd out5 pgnd3 out6 234567891011121314 28 27 26 25 24 23 22 21 20 19 18 17 16 15 c ss2 i i2 fb2 n.c. c ss1 i i1 fb1 c ss6 i i6 fb6 agnd1 c ss5 i i5 fb5 43 44 45 46 47 48 49 50 51 52 53 54 55 56 lv dd cs sda scl shdnb test3 test1 test2 dcon i i9 out9 i i8 out8 i i7 agnd2 c dly v ref r t c t c ss4 i i4 fb4 v dd n.c. c ss3 i i3 fb3 n.c. data sheet s17102ej2v0ds 4 pd16908 3. pin functions (1/2) pin no. symbol pin name i/o description 1 out7 output 7 output output of ch7 series regulator (e/a) 2 bv dd buffer regulator power supply power supply powe r supply for series r egulator (ch7 to ch9) 3 pgnd4 power ground ground power ground 4 out4 output 4 output output for driving power mos fet of ch4 5 pgnd2 power ground ground power ground 6 out3 output 3 output output for driving power mos fet of ch3 7 pv dd power supply for output buffer stage power supply power supply for output buffer stage of ch1 to ch4 8 out2 output 2 output output for driving power mos fet of ch2 9 pgnd1 power ground ground power ground 10 out1 output 1 output output for driving power mos fet of ch1 11 npv dd power supply for output buffer stage power supply power supply for output buffer stage of ch5 and ch6 12 out5 output 5 output output for driving power mos fet of ch5 13 pgnd3 power ground ground power ground 14 out6 output 6 output output for driving power mos fet of ch6 15 fb5 feedback output feedback of ch5 e/a 16 i i5 inversion input input inversion input of ch5 e/a 17 c ss5 soft start capacitance 5 output capac itance connection pin for ch5 soft start 18 agnd1 analog ground ground analog ground 19 fb6 feedback output feedback of ch6 e/a 20 i i6 inversion input input inversion input of ch6 e/a 21 c ss6 soft start capacitance 6 output capac itance connection pin for ch6 soft start 22 fb1 feedback output feedback of ch1 e/a 23 i i1 inversion input input inversion input of ch1 e/a 24 c ss1 soft start capacitance 1 output capac itance connection pin for ch1 soft start 25 n.c. ? ? leave open, or short to gnd or lv dd 26 fb2 feedback output feedback of ch2 e/a 27 i i2 inversion input input inversion input of ch2 e/a 28 c ss2 soft start capacitance 2 output capac itance connection pin for ch2 soft start 29 n.c. ? ? leave open, or short to gnd or lv dd 30 fb3 feedback output feedback of ch3 e/a 31 i i3 inversion input input inversion input of ch3 e/a 32 c ss3 soft start capacitance 3 output capac itance connection pin for ch3 soft start 33 n.c. ? ? leave open, or short to gnd or lv dd 34 v dd power supply power supply po wer supply for dc-dc converter 35 fb4 feedback output feedback of ch4 e/a 36 i i4 inversion input input inversion input of ch4 e/a 37 c ss4 soft start capacitance 4 output capac itance connection pin for ch4 soft start data sheet s17102ej2v0ds 5 pd16908 (2/2) pin no. symbol pin name i/o description 38 c t timing capacitor output capacitor connection for triangular wave generation 39 r t timing resistance output resistance connection for triangular wave generation 40 v ref reference voltage output power supply for reference voltage 41 c dly short-circuit protection circuit delay capacitance output capacitor connection for timer latch 42 agnd2 analog ground ground analog ground 43 lv dd power supply for control logic power supply power supply for control logic 44 cs chip select input chip select 45 sda serial data input input serial data input for controlling each output 46 scl serial clock input input serial clock input for controlling each output 47 shdnb shut-down input input shut down the ic 48 test3 test 3 input short to lv dd 49 test1 test 1 input short to gnd 50 test2 test 2 input short to gnd 51 dcon output turn-on control input output of the channel selected by serial data is switched on. 52 i i9 inversion input input inversion input of ch9 e/a 53 out9 output 9 output output of ch9 series regulator (e/a) 54 i i8 inversion input input inversion input of ch8 e/a 55 out8 output 8 output output of ch8 series regulator (e/a) 56 i i7 inversion input input inversion input of ch7 e/a data sheet s17102ej2v0ds 6 pd16908 4. electrical specifications absolute maximum ratings (unless otherwise specified, t a = 25c) parameter symbol condition rating unit power supply voltage v dd ? 0.5 to +6 v power supply voltage for output buffer stage 1 pv dd (ch1 to ch4) ? 0.5 to +6 v power supply voltage for output buffer stage 2 npv dd (ch5 and ch6) ? 0.5 to +6 v buffer regulator power supply voltage bv dd ? 0.5 to +6 v control logic power supply voltage lv dd ? 0.5 to +6 v analog input pin voltage v ain fb, i i ? 0.5 to +6 v control logic input voltage v clin shdnb, dcon, sda, scl, cs ? 0.5 to lv dd + 0.5 v output current (dc) 1-6 i o(dc)1-6 out1 to out6 20 ma output current (pulse) 1-6 i o(pulse)1-6 out1 to out6 200 ma output current (dc) 7-9 i o(dc)7-9 out7 to out9 20 ma total power dissipation p t glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15% 0.8 w operating ambient temperature t a ? 30 to +75 c operating junction temperature t j ? 30 to +125 c storage temperature t stg ? 55 to +125 c caution product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. data sheet s17102ej2v0ds 7 pd16908 recommended operating conditions (unless otherwise specified, t a = 25 c) parameter symbol condition min. typ. max. unit power supply voltage v dd 2.7 3.3 5.5 v power supply voltage for output buffer stage 1 pv dd (ch1 to ch4) 2.7 3.3 5.5 v power supply voltage for output buffer stage 2 npv dd (ch5 and ch6) 2.7 3.3 5.5 v buffer regulator power supply voltage bv dd 3.0 3.3 5.5 v control logic power supply voltage lv dd 2.7 3.3 3.6 v control logic input voltage v clin shdnb, dcon, sda, scl, cs 2.7 3.3 3.6 v operating frequency f osc 200 700 800 khz timing capacitance c ct capacitance connected to c t 60 240 pf timing resistance r rt resistance connected to r t 5.1 22 k ? serial clock period t prd 10 s scl waiting time t (scl-cs) 500 ns cs waiting time t (cs-scl) 50 ns sda set-up time t setup 50 ns sda hold time t hold 50 ns scl high-pulse time t pw 2 s scl low-pulse time t nw 2 s t (scl-cs) t setup t hold t pw t prd t nw t (cs-scl) 50% 50% d 1 d 2 d 3 d 4 d 8 50% 50% 50% 50% 50% 50% cs sda scl data sheet s17102ej2v0ds 8 pd16908 electrical characteristics (unl ess otherwise specified, v dd = npv dd = pv dd = lv dd = bv dd = 3.3 v, f osc = 700 khz, t a = 25 c) (1/2) overall parameter symbol condition min. typ. max. unit shut-down current i dd(shd) shdnb = l, v dd + npv dd + pv dd + bv dd + lv dd 5 8 a standby current i dd(sb) dcon = l, shdnb = h, v dd + npv dd + pv dd + bv dd + lv dd 2.04 3.75 ma circuit operation current 1 i dd v dd 2.04 3.75 ma circuit operation current 2 pi dd pv dd , cl = 150 pf, fb = v dd 3.0 5.7 ma circuit operation current 3 npi dd npv dd , cl = 150 pf, fb = agnd 0.96 1.8 ma circuit operation current 4 bi dd bv dd , no-load, i i = bv dd 180 345 a circuit operation current 5 li dd lv dd 24 45 a triangular wave oscillator block parameter symbol condition min. typ. max. unit oscillation frequency setting accuracy f osc c ct = 150 pf, r rt = 11 k ? ? 10 +10 % triangular wave low-level voltage v th(l) 1.1 v triangular wave high-level voltage v th(h) 1.8 v reference voltage block parameter symbol condition min. typ. max. unit reference voltage v ref i ref = 1 ma 1.97 2.0 2.03 v maximum output current i ref 1 2 ma pwm comparator block parameter symbol condition min. typ. max. unit maximum duty 1-4 d max.1-4 ch1 to ch4 85 % maximum duty 5-6 d max.5-6 ch5 and ch6 85 % undervoltage lockout circuit block parameter symbol condition min. typ. max. unit operation start voltage at power application v dd(l-h) 1.01 1.45 1.89 v operation stop voltage v dd(h-l) 0.89 1.27 1.65 v hysteresis width v h 5 60 mv short-circuit protection circuit block parameter symbol condition min. typ. max. unit fb detection voltage 1-4 v th(fb)1-4 fb (ch1 to ch4) 1.9 2 2.1 v fb detection voltage 5-6 v th(fb)5-6 fb (ch5 and ch6) 0.76 0.8 0.84 v dly detection voltage v th(dly) c dly 0.76 0.8 0.84 v short-circuit source current i dly 1 2 4 a data sheet s17102ej2v0ds 9 pd16908 (2/2) soft start block parameter symbol condition min. typ. max. unit c ss detection voltage 1-4 v th(css)1-4 c ss1 to c ss4 1.47 1.55 1.63 v c ss detection voltage 5-6 v th(css)5-6 c ss5 and c ss6 0.79 1.35 1.59 v charge current i css 1 2 4 a output block (ch1 to ch6) parameter symbol condition min. typ. max. unit output turn-on resistance-p r onp i o = 15 ma 10 15 ? output turn-off resistance-n r onn i o = 15 ma 10 15 ? e/a block (ch1 to ch4) parameter symbol condition min. typ. max. unit e/a1 input threshold voltage v ith1 ch1out control bit is fixed to default setting (d [0:5] = 000000), offset is not included. 0.666 0.680 0.694 v e/a2 input threshold voltage v ith2 ch2out control bit is fixed to default setting (d [0:5] = 000000), offset is included. 0.680 0.700 0.720 v e/a3 input threshold voltage v ith3 ch3out control bit is fixed to default setting (d [0:5] = 000000), offset is not included. 0.666 0.680 0.694 v e/a4 input threshold voltage v ith4 offset is not included. 0.980 1.000 1.020 v e/a1 input offset voltage v ioff1 v ref = 2 v 0 40 mv e/a3 input offset voltage v ioff3 0 40 mv e/a4 input offset voltage v ioff4 0 40 mv e/a block (ch5 and ch6) parameter symbol condition min. typ. max. unit e/a5 input threshold voltage v ith5 offset is not included. 0.980 1.000 1.020 v e/a6 input threshold voltage v ith6 0.980 1.000 1.020 v e/a5 input offset voltage v ioff5 v ref = 2 v 0 40 mv e/a6 input offset voltage v ioff6 0 40 mv e/a block (ch7 to ch9) parameter symbol condition min. typ. max. unit e/a7 input threshold voltage v ith7 offset is not included. 0.980 1.000 1.020 v e/a8 input threshold voltage v ith8 0.980 1.000 1.020 v e/a9 input threshold voltage v ith9 0.980 1.000 1.020 v e/a7 input offset voltage v ioff7 v ref = 2 v ? 10 30 mv e/a8 input offset voltage v ioff8 ? 10 30 mv e/a9 input offset voltage v ioff9 ? 10 30 mv i/o differential voltage v diff bv dd ? out7 to out9, i o = 10 ma 1 v control logic block and serial interface block parameter symbol condition min. typ. max. unit high-level input voltage v ih(l) shdnb, dcon, sda, scl, cs lv dd x 0.8 v low-level input voltage v il(l) shdnb, dcon, sda, scl, cs lv dd x 0.2 v input leak current i l shdnb, dcon, sda, scl, cs, v in = agnd to lv dd 1 v data sheet s17102ej2v0ds 10 pd16908 5. timing chart lv dd shdnb v ref c t dcon out7 to out9 out5, out6 out1 to out4 cs sda scl v dd pv dd npv dd bv dd power supply input signal output signal data sheet s17102ej2v0ds 11 pd16908 6. i/o pin equivalent circuit (protection circuit) pin no. symbol internal circuit specifi ed protection power supply connection (refer to figure 6 ? 1 ) configuration element v dd side gnd side 1 out7 analog output output protection 1 bv dd agnd, pgnd 2 bv dd power supply power supply protection bv dd agnd, pgnd 3 pgnd4 ground power supply protection v dd , pv dd , npv dd , lv dd pgnd 4 out4 logic output output protection 1 pv dd agnd, pgnd 5 pgnd2 ground power supply protection v dd , pv dd , npv dd , lv dd pgnd 6 out3 logic output output protection 1 pv dd agnd, pgnd 7 pv dd power supply power supply protection pv dd agnd, pgnd 8 out2 logic output output protection 1 pv dd agnd, pgnd 9 pgnd1 ground power supply protection v dd , pv dd , npv dd , lv dd agnd, pgnd 10 out1 logic output output protection 1 pv dd agnd, pgnd 11 npv dd power supply power supply protection npv dd agnd, pgnd 12 out5 logic output output protection 1 npv dd agnd, pgnd 13 pgnd3 ground power supply protection v dd , pv dd , npv dd , lv dd pgnd 14 out6 logic output output protection 1 npv dd agnd, pgnd 15 fb5 analog output output protection 1 v dd agnd 16 i i5 gate input input protection 1 v dd agnd 17 c ss5 analog output output protection 1 v dd agnd 18 agnd1 ground power supply protection v dd , pv dd , npv dd , lv dd agnd 19 fb6 analog output output protection 1 v dd agnd 20 i i6 gate input input protection 1 v dd agnd 21 c ss6 analog output output protection 1 v dd agnd 22 fb1 analog output output protection 1 v dd agnd 23 i i1 gate input input protection 1 v dd agnd 24 c ss1 analog output output protection 2 v dd agnd 25 n.c. ? ? ? ? 26 fb2 analog output output protection 1 v dd agnd 27 i i2 gate input input protection 1 v dd agnd 28 c ss2 analog output output protection 2 v dd agnd 29 n.c. ? ? ? ? 30 fb3 analog output output protection 1 v dd agnd 31 i i3 gate input input protection 1 v dd agnd 32 c ss3 analog output output protection 2 v dd agnd 33 n.c. ? ? ? ? 34 v dd power supply power supply protection v dd agnd, pgnd 35 fb4 analog output output protection 1 v dd agnd 36 i i4 gate input input protection 1 v dd agnd 37 c ss4 analog output output protection 2 v dd agnd 38 c t analog output output protection 2 v dd agnd 39 r t analog output output protection 2 v dd agnd 40 v ref analog output output protection 2 v dd agnd data sheet s17102ej2v0ds 12 pd16908 2/2 pin no. symbol internal circuit specifi ed protection power supply connection (refer to figure 6 ? 1 ) configuration element v dd side gnd side 41 c dly analog output output protection 2 v dd agnd 42 agnd2 ground power supply protection v dd , pv dd , npv dd , lv dd agnd 43 lv dd power supply power supply protection lv dd agnd, pgnd 44 cs gate input input protection 1 lv dd agnd 45 sda gate input input protection 1 lv dd agnd 46 scl gate input input protection 1 lv dd agnd 47 shdnb gate input input protection 1 lv dd agnd 48 test3 gate input input protection 1 lv dd agnd 49 test1 gate input input protection 1 lv dd agnd 50 test2 gate input input protection 1 lv dd agnd 51 dcon gate input input protection 1 lv dd agnd 52 i i9 gate input input protection 1 bv dd agnd 53 out9 analog output output protection 1 bv dd agnd, pgnd 54 i i8 gate input input protection 1 bv dd agnd 55 out8 analog output output protection 1 bv dd agnd, pgnd 56 i i7 gate input input protection 1 bv dd agnd figure 6 ? 1. input protection 1 v dd side gnd side output protection 1 v dd side gnd side output protection 2 v dd side gnd side power supply protection v dd side gnd side data sheet s17102ej2v0ds 13 pd16908 7. control logic block 7.1 shdnb pin (pin no. 47) the internal circuits (e/a, pwm comparator, triangular wave oscillator) are stopped by the shdnb pin and the serial interface registers are reset. t he capacitor connec ted between the c ss1 to c ss6 pins also discharges. shdnb state of ic serial interface l shut down (out1 to out4 = fixed to gnd, out5 and out6 = fixed to v dd , and out7 to out9 = fixed to gnd) input disable h on input enable 7.2 dcon pin (pin no. 51) the outputs are switched off by the dcon pin while the internal circuits are operating (seria l interface input possible). the capacitor connected between the c ss1 to c ss6 pins also discharges. dcon state of ic serial interface l standby (all channel output turns off, and the internal circuits operate.) (out1 to out4 = fixed to gnd, out5 and out6 = fixed to v dd , and out7 to out9 = fixed to gnd) h the channel specified by on/off control bit of the serial interface turns on. input enable data sheet s17102ej2v0ds 14 pd16908 8. serial interface block 8.1 control data (default = all ?0?) data is the turn of d 11 , d 10 , d 9 , ??? , and d 0 , and please input it. msb d 11 d 10 first last d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 lsb d 0 d 5 d 4 d 3 d 2 d 1 d 0 ? ? ? 000000 000 d 11 d 10 d 9 000 001 010 011 100 101 110 111 001 111110 111111 output voltage input data output output voltage control bit unused unused on/off control 1 on/off control 2 unused unused ch1 output voltage ch1out ch7out to ch9out ch1out to ch6out ch2out ch3out ch2 output voltage ch3 output voltage refer to 8.2 details of output voltage control bits . output voltage control bit data sheet s17102ej2v0ds 15 pd16908 8.2 details of output voltage control bits input data configuration of input address control bit d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 unused ch1 output voltage table 8 ? 1. ch1 output voltage (ch1out) control bit d 5 d 4 d 3 d 2 d 1 d 0 e/a1 threshold volta g e typ. v ith1 [v] 000000 0.68 000001 0.69 000010 0.70 000011 0.71 000100 0.72 000101 0.73 000110 0.74 000111 0.75 001000 0.76 001001 0.77 001010 0.78 001011 0.79 001100 0.80 001101 0.81 001110 0.82 001111 0.83 010000 0.84 010001 0.85 010010 0.86 010011 0.87 010100 0.88 010101 0.89 010110 0.90 010111 0.91 011000 0.92 011001 0.93 011010 0.94 011011 0.95 011100 0.96 011101 0.97 011110 0.98 011111 0.99 100000 1.00 100001 1.01 100010 1.02 100011 1.03 100100 1.04 100101 1.05 100110 1.06 100111 1.07 101000 1.08 101001 1.09 101010 1.10 101011 1.11 101100 1.12 101101 1.13 101110 1.14 101111 1.15 110000 1.16 110001 1.17 110010 1.18 110011 1.19 110100 1.20 110101 1.21 110110 1.22 110111 1.23 111000 1.24 111001 1.25 111010 1.26 111011 1.27 111100 1.28 111101 1.29 111110 1.30 111111 1.31 caution the output voltage value becomes ch1out ? v ith1 x ( (r11 + r12) /r12). data sheet s17102ej2v0ds 16 pd16908 input data configuration of input address control bit d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 unused ch2 output voltage table 8 ? 2. ch2 output voltage (ch2out) control bit d 5 d 4 d 3 d 2 d 1 d 0 e/a2 threshold voltagetyp. v ith2 [v] 000000 0.68 000001 0.69 000010 0.70 000011 0.71 000100 0.72 000101 0.73 000110 0.74 000111 0.75 001000 0.76 001001 0.77 001010 0.78 001011 0.79 001100 0.80 001101 0.81 001110 0.82 001111 0.83 010000 0.84 010001 0.85 010010 0.86 010011 0.87 010100 0.88 010101 0.89 010110 0.90 010111 0.91 011000 0.92 011001 0.93 011010 0.94 011011 0.95 011100 0.96 011101 0.97 011110 0.98 011111 0.99 100000 1.00 100001 1.01 100010 1.02 100011 1.03 100100 1.04 100101 1.05 100110 1.06 100111 1.07 101000 1.08 101001 1.09 101010 1.10 101011 1.11 101100 1.12 101101 1.13 101110 1.14 101111 1.15 110000 1.16 110001 1.17 110010 1.18 110011 1.19 110100 1.20 110101 1.21 110110 1.22 110111 1.23 111000 1.24 111001 1.25 111010 1.26 111011 1.27 111100 1.28 111101 1.29 111110 1.30 111111 1.31 caution the output voltage value becomes ch2out ? v ith2 x ( (r21 + r22) /r22). data sheet s17102ej2v0ds 17 pd16908 input data configuration of input address control bit d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 unused ch3 output voltage table 8 ? 3. ch3 output voltage (ch3out) control bit d 5 d 4 d 3 d 2 d 1 d 0 e/a3 threshold voltage typ. v ith3 [v] 000000 0.68 000001 0.69 000010 0.70 000011 0.71 000100 0.72 000101 0.73 000110 0.74 000111 0.75 001000 0.76 001001 0.77 001010 0.78 001011 0.79 001100 0.80 001101 0.81 001110 0.82 001111 0.83 010000 0.84 010001 0.85 010010 0.86 010011 0.87 010100 0.88 010101 0.89 010110 0.90 010111 0.91 011000 0.92 011001 0.93 011010 0.94 011011 0.95 011100 0.96 011101 0.97 011110 0.98 011111 0.99 100000 1.00 100001 1.01 100010 1.02 100011 1.03 100100 1.04 100101 1.05 100110 1.06 100111 1.07 101000 1.08 101001 1.09 101010 1.10 101011 1.11 101100 1.12 101101 1.13 101110 1.14 101111 1.15 110000 1.16 110001 1.17 110010 1.18 110011 1.19 110100 1.20 110101 1.21 110110 1.22 110111 1.23 111000 1.24 111001 1.25 111010 1.26 111011 1.27 111100 1.28 111101 1.29 111110 1.30 111111 1.31 caution the output voltage value becomes ch3out ? v ith3 x ( (r31 + r32) /r32). data sheet s17102ej2v0ds 18 pd16908 input data configuration of input address control bit d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 unused on/off control 1 1 1 0 unused on/off control 2 ? on/off control bit 1 d 5 d 4 d 3 d 2 d 1 d 0 input data output of ch6 output of ch5 output of ch4 output of ch3 output of ch2 output of ch1 0 on 1 off (e/a and pwm operation stop) ? on/off control bit 2 d 5 d 4 d 3 d 2 d 1 d 0 input data unused unused unused output of ch9 output of ch8 output of ch7 0 ? on 1 ? off (e/a and pwm operation stop) data sheet s17102ej2v0ds 19 pd16908 8.3 serial correspondence timing sda msb d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 lsb read at the rising high-level load scl cs ? the 12-bit serial data inputted by the sda pin is loaded to t he shift register at the risi ng edge of the signal inputted to the scl pin. the loaded data is loaded to the shift register at the rising edge of the signal inputted to the cs pin. be sure to fix the signal input to the scl pin to low leve l at the rising and falling edges of the signal input to the cs pin. ? if the data which is loaded to shift register while the cs pin is low level is less than 12 bits, the loaded data is cancelled. if the loaded data is more than 12 bits, the 12-bit data is valid in the last of the loaded data. data sheet s17102ej2v0ds 20 pd16908 9. typical characteristics (unless otherwise specified, v dd = npv dd = pv dd = l v dd = b v dd = 3.3 v, f osc = 700 khz, t a = 25c, reference value) v ref vs. v dd v ref vs. t a v ref - v 1.9 1.95 2 2.05 2.1 2.533.544.555.56 v dd - v v ref - v 1.9 1.95 2 2.05 2.1 -40 -20 0 20 40 60 80 t a - c f osc vs. v dd f osc vs. t a f osc - khz 500 600 700 800 900 1000 2.533.544.555.56 v dd - v f osc - khz 500 600 700 800 900 1000 -40 -20 0 20 40 60 80 t a - c f osc vs. r rt c ct = 68 pf 150 pf 220 pf 330 pf frequency- khz 1 10 100 1000 10000 1 10 100 1000 r rt - k ? data sheet s17102ej2v0ds 21 pd16908 d max.1-4 vs. v dd d max.1-4 vs. t a d max.1-4 - % 50 60 70 80 90 100 2.533.544.555.56 v dd - v d max.1-4 - % 50 60 70 80 90 100 -40-20 0 20406080 t a - c d max.5-6 vs. v dd d max.5-6 vs. t a d max.5-6 - % 50 60 70 80 90 100 2.5 3 3.5 4 4.5 5 5.5 6 v dd - v d max.5-6 - % 50 60 70 80 90 100 -40-20 0 20406080 t a - c i dly vs. v dd i dly vs. t a i dly - a 0 2 4 6 8 2.533.544.555.56 v dd - v i dly - a 0 2 4 6 8 -40 -20 0 20 40 60 80 t a - c data sheet s17102ej2v0ds 22 pd16908 i css vs. v dd i css vs. t a i css - a 0 2 4 6 8 2.533.544.555.56 v dd - v i css - a 0 2 4 6 8 -40-20 0 20406080 t a - c data sheet s17102ej2v0ds 23 pd16908 10. operation explanation of each block 10.1 reference voltage circuit block the reference voltage circuit block outputs reference vo ltage (2.0 v typ.) by which temperature compensation is carried out by supplying voltage by the v dd (no. 34) pin. the reference volt age is used as the re ference voltage of each internal circuit, and can be extracted to outside by the v ref (no. 40) pin to 1 ma typ.. 10.2 triangular wave oscillator block the triangular wave oscillator block performs self-excit ed oscillation using the timing capacitance and timing resistor externally attached to the c t (no. 38) pin and r t (no. 39) pin, respectively, and outputs a symmetric triangular wave with an amplitude of 1.1 to 1.8 v typ. to the c t (no. 38) pin. this triangular wave is supplied to the inversion input pin of the pwm comparator. 10.3 e/a block the input threshold voltage of e/a is t he voltage set by the output vo ltage control bit of the seri al interface for e/a1 to e/a3 (default = all zero; 0.68 v typ.), and 1.0 v typ. for e/a4 to e/a9. note that e/a7 to e/a9 operate as a series regulator. 10.4 pwm comparator block the pwm comparator compares the triangular wave signal and e/a output signal (or maximum duty) and controls the output on duty. 10.5 output circuit block the output circuit block of ch1 to ch6 is of push-pull configur ation and can directly drive a power mos fet. the output current capacity is 200 ma max. fo r pulse output and 20 ma max. for dc output. the output current capacity of the output circuit block of ch7 to ch9 is 20 ma max. for dc output 10.6 undervoltage lockout circuit block the undervoltage lockout circuit block shuts down the ic if the power supply voltage is insufficient at power application or shut down in order to prevent malfunction of the ic. data sheet s17102ej2v0ds 24 pd16908 10.7 soft start block of the step-up dc-dc converter output (ch1 to ch4) ch1 is soft-started by a capacitor connected to the c ss1 (no. 24) pin. also, ch2 to c h4 are respectively soft-started by a capacitor connected to the c ss2 (no. 28) pin, c ss3 (no. 32) pin, and c ss4 (no. 37) pin. soft start is executed by chargi ng the capacitor connected to each c ss pin and gradually increas ing the voltage at the c ss pin. on starting the ic, the voltage at each c ss pin is connected to the non-invert ed input of e/a. soft start is executed by increasing the non-inverted input voltage of e/a from 0 v and gradually pr olonging the output on duty. ( figure 10 ? 1 and 10 ? 2 ) figure 10 ? 1. dtc c t fb1 to fb4 dtc fb1 to fb4 threshold voltage of e/a1 to e/a4 c ss1 to c ss4 out1 to out4 v out (outputs of ch1 to ch4) power on 0 v on on on on on on on on on 1.1 v 1.8 v (v dd ) v setting voltage v th(css)1-4 = 1.55 v figure 10 ? 2. dtc c t c dly ch1 to ch3: 0.68 v ch4: 1 v ? + + ? + ? 41 38 fb1 to fb4 c ss1 to c ss4 i i1 to i i4 i css v out (outputs of ch1 to ch4) e/a1 to e/a4 pwm1 to pwm4 out1 to out4 soft start circuit triangular wave oscillator timer latch short-circuit protection circuit undervoltage lockout circuit data sheet s17102ej2v0ds 25 pd16908 10.8 soft start block of the polarity-inverted dc-dc converter output (ch5 and ch6) ch5 is soft-started by a capacitor connected to the c ss5 (no. 17) pin. also, ch6 is soft-started by a capacitor connected to the c ss6 (no. 21) pin. soft start is executed by chargi ng the capacitor connected to each c ss pin and gradually increas ing the voltage at the c ss pin. the c ss pin voltage is connected to the pw m non-inverted input (dtc) via a 200 k ? resistor. at startup, raising the pwm non-inverted input (dtc ) voltage from about 0.4 gradually lengt hens the output on duty, causing a soft start ( figure 10 ? 3 and 10 ? 4 ). note that if the dtc voltage and fb voltage are switched while the output on duty is still small (less than 50%) following a soft start, inrush current may o ccur at the point of switching. in th is case, suppress the inrush current by either raising the operati ng frequency or increasing the inductance of the coil used by the dc-dc converter. figure 10 ? 3. dtc c t fb5, fb6 dtc fb5, fb6 c ss5 , c ss6 out5, out6 0 v 0 v about 0.4 v on on on on on on on on on on on 1.1 v v th(css)5-6 = 1.35 v typ. 1.8 v 1.75 v (v dd ) v v out (outputs of ch5 and ch6) power on setting voltage figure 10 ? 4. dtc dtc c t c dly fb5, fb6 c ss5 , c ss6 1 v 1.15 v a e d sw 200 k ? i i5 , i i6 i css v ref v out (outputs of ch5 and ch6) e/a5, e/a6 pwm5, pwm6 out5, out6 ? + ? + ? 41 38 c ss5 , c ss6 0 v about 0.4 v about 1.35 v 1.75 v (v dd ) v about 0.4 v 1.15 v 1.75 v b c sw soft start circuit triangular wave oscillator timer latch short-circuit protection circuit undervoltage lockout circuit sw switches from d to e when the fb voltage becomes higher than point a. sw switches from b to c as soon as voltage of a becomes 1.75 v. data sheet s17102ej2v0ds 26 pd16908 10.9 short-circuit protection circuit block (timer latch type) if the voltage of ch1 to ch4, which are the step-up dc-dc converte r outputs, drops, the voltage of the inversion input pin of the e/a, which is feeding back the output, also drops, and the e/a output (fb) is stepped up. if the voltage of this e/a output (fb) reaches or ex ceeds the fb detection vo ltage of the short-circuit protection circuit (v th(fb)1-4 = 2.0 v typ.), the timer circuit starts operat ing and the capacitor connected to the c dly (no. 41) pin starts charging. when the voltage of the capac itor connected the c dly (no. 41) pin reaches the c dly protection voltage (v th(dly) = 0.8 v typ.), all the outputs of t he ic are latched to off ( figure 10 ? 5 and 10 ? 6 ). if the voltage of ch5 and ch6, which are the polarity-inverted dc-dc converter outputs, is stepped up, the voltage of the inversion input pin of t he e/a, which is feeding back the output, is also stepped up, and the e/a output (fb) is stepped down. if the voltage of th is e/a output (fb) falls below the fb detection voltage of the short-circuit protection circuit (v th(fb)5-6 = 0.8 v typ.), the timer circuit starts operating and the capacitor connected to the c dly (no. 41) pin starts charging. when the voltage of the capacit or connected to the c dly (no. 41) pin reaches the c dly detection voltage (v th(dly) = 0.8 v typ.), all the outputs of the ic are latched to off ( figure 10 ? 5 and 10 ? 7 ). as long as the e/a output (fb) of any of ch1 to ch6 is at least the fb detec tion voltage of the shor t-circuit protection circuit, the capacitor connected to the c dly (no. 41) pin continues to charge. ( figure 10 ? 8 ) to reset the latch circuit when the short-circuit prot ection circuit is activated, decrease the supply voltage (v dd ) to the operation stop voltage level (v dd(h-l) = 1.39 v typ.), or set the shdnb (no. 47) pin or dcon (no. 51) pin to low level. figure 10 ? 5. 0.8 v c dly i dly fb1 i i1 e/a1 ? + + ? + ? 41 22 23 fb2 i i2 e/a2 ? + 26 27 fb3 i i3 e/a3 ? + 30 31 fb4 i i4 e/a4 2.0 v 0.8 v ? + 35 36 + ? + ? + ? fb5 i i5 v ref v ref e/a5 ? + 15 16 fb6 i i6 e/a6 ? + 19 20 + ? + ? (output of ch1) ch1scp comparator (output of ch2) ch2scp comparator (output of ch3) ch3scp comparator (output of ch4) (output of ch5) (output of ch6) ch4scp comparator ch5scp comparator ch6scp comparator scp signal the capacitor connected to c ss1 to c ss6 is discharged. the capacitor connected to c dly starts charging when the fet switches from on to off, and the comparator outputs the scp signal when c dly reaches 0.8 v. all the outputs of ch1 to ch6 makes it stop. latch circuit comparator a channel that is switched off by the serial interface is not involved in the timer latch function. data sheet s17102ej2v0ds 27 pd16908 figure 10 ? 6. dtc c t fb1 to fb4 fb1 to fb4 c dly out1 to out4 1.1 v 1.8 v 2 v 0.8 v the short-circuit protection circuit latches the outputs at 0.8 v and the outpus are switched off. the outputs of ch1 to ch4 are load-short-circuited. the outputs of ch1 to ch4 are switched off. stop of operation v out (outputs of ch1 to ch4) the short-circuit protection circuit causes the capacitor to start charging when fb1 to fb4 = 2.0 v or higher. figure 10 ? 7. c t fb5, fb6 c dly out5, out6 v out (outputs of ch5 and ch6) 1.1 v 1.8 v 0.8 v 0.8 v dtc on fb5, fb6 the short-circuit protection circuit latches the outputs at 0.8 v and the outpus are switched off. the outputs of ch5 and ch6 are load-short-circuited. the outputs of ch5 and ch6 are switched off. stop of operation the short-circuit protection circuit causes the capacitor to start charging when fb5 and fb6 = 0.8 v or less. figure 10 ? 8. 0.8 v 2 v 0.8 v c t fb5, fb6 c dly fb5, fb6 fb1 to fb4 fb1 to fb4 the short-circuit protection circuit latches the outputs at 0.8 v and the outpus are switched off. if all the outputs of ch1 to ch6 fall below the fb ditection voltage, even momentarily, charge of the capacitor connected to c dly is reset. as long as one of ch1 to ch6 is at least the fb ditection voltage, the capacitor connected to c dly contunues to charge. data sheet s17102ej2v0ds 28 pd16908 11. notes on use 11.1 method of setting output voltage the method of setting the output vo ltage of ch1 to ch4 is shown in figure 11 ? 1 , the method of setting the output voltage of ch5 and ch6 is shown in figure 11 ? 2 , and the method of setti ng the output voltage of ch5 to ch7 is shown in figure 11 ? 3 . the output voltage can be calculated by using the expression in the figure. figure 11 ? 1. the method of setting the output voltage of the step-up circuit of ch1 to ch4 v out = (1 + r1/r2) x v ith fb1 to fb4 v ith i i1 to i i4 e/a1 to e/a4 ? + r1 r2 v out (outputs of ch1 to ch4) caution v ith of ch1 to ch3 depends on the serial interface. v ith of ch4 is 1.0 v typ.. figure 11 ? 2. the method of setting the output voltage of the polarity-inverted circuit of ch5 and ch6 v out = (1 + r1/r2) x 1.0 ? r2/r1 x v ref fb5, fb6 1.0 v typ. i i5 , i i6 v ref (reference voltage/40-pin) ? v out (outputs of ch5 and ch6) e/a5, e/a6 ? + r1 r2 figure 11 ? 3. the method of setting the output voltage of ch7 to ch9 v out = (1 + r1/r2) x 1.0 out7 to out9 1.0 v typ. i i7 to i i9 ? + r1 r2 data sheet s17102ej2v0ds 29 pd16908 11.2 method of handling pins of unused channels figure 11 ? 4 to 11 ? 8 show how to handle the pins when not using ch1 to ch3, ch5 and ch6, ch7 to ch9, and the serial interface, respectively. figure 11 ? 4. handling of pins when not using ch1 to ch3 v dd c ss1 to c ss3 fb1 to fb3 i i1 to i i3 e/a1 to e/a3 pwm1 to pwm3 out1 to out3 ? + + ? ? 34 soft start circuit triangular wave oscillator timer latch short-circuit protection circuit undervoltage lockout circuit figure 11 ? 5. handling of pins when not using ch4 v dd c ss4 fb4 i i4 e/a4 pwm4 out4 ? + + ? ? 34 35 36 37 4 soft start circuit triangular wave oscillator timer latch short-circuit protection circuit undervoltage lockout circuit figure 11 ? 6. handling of pins when not using ch5 and ch6 v dd c ss5 , c ss6 fb5, fb6 i i5 , i i6 e/a5, e/a6 pwm5, pwm6 out5, out6 ? + + ? ? 34 soft start circuit triangular wave oscillator timer latch short-circuit protection circuit undervoltage lockout circuit data sheet s17102ej2v0ds 30 pd16908 figure 11 ? 7. handling of pins when not using ch7 to ch9 ? + i i7 to i i9 e/a7 to e/a9 out7 to out9 figure 11 ? 8. handling of pins when not using the serial interface lv dd 43 sc 44 sda 45 scl 46 serial interface block 11.3 method of setting oscillation frequency the oscillation frequency can be arbitrarily set by the timing resistor (r rt ) connected to the r t (no. 39) pin, and the timing capacitance (c ct ) value connected to the c t (no. 38) pin. expression <1> shows an approximate expression of the oscillation frequency (f osc ). however, because this is an approximate expression, be sure to c heck the frequency on the act ual device, especially when using a high frequency. f osc [hz] = 1.43/ (r rt [ ? ] x c ct [f]) ?????? <1> 11.4 method of setting soft-start time expression <2> shows an approximate expression of the soft-start charge time of ch1 to ch4, t ss1 to t ss4 . t ss1 to t ss4 [s] = 0.775 x c ss [ f] ?????? <2> expression <3> shows an approximate expression of the soft-start charge time of ch5 and ch6, t ss5 and t ss6 . t ss5 and t ss6 [s] = 0.675 x c ss [ f] ?????? <3> note, however, that the startup characteristics of each channel differ depending on the load condi tions of that channel, as mentioned in 10.7 soft start block of the step-up dc-dc converter output (ch1 to ch4) (figure 10 ? 1), and 10.8 soft start block of the polarity-inverted dc-dc converter output (ch5 and ch6) (figure 10 ? 3) ,so t ss does not equal the rise time of t he output voltage of each channel. ther efore, be sure to check the soft- start time on the actual device. data sheet s17102ej2v0ds 31 pd16908 11.5 method of calculating delay time of short-circuit protection circuit expression <4> shows an approximate expression of the short-circuit protection circuit delay time, t dly . t dly [s] = 0.4 x c dly [ f] ?????? <4> 11.6 method of handling pins when short-circuit protection circuit is unused when the short-circuit protecti on circuit is unused, connected the c dly (no. 41) pin to the agnd (no. 18 and 42) pin. 11.7 method of preventing malfunction of short-circuit protection circuit if noise is superimposed on the c dly (no. 41) pin, the internal latch circ uit may malfunction, causing the outputs to stop operating. to prevent this kind of malfuncti on, reduce the wiring impedance between the c dly (no. 41) pin and the agnd (no. 18 and 42) pins, and take measures so t hat noise is not superimposed on the c dly (no. 41) pin. note that if the soft-start time is longer than the short-circuit protection ci rcuit may operate befor e the output of the channel rises. therefore, be sure to determine the short-circuit protection circ uit delay time on the actual device. 11.8 notes on actual pattern wiring when actually wiring the pattern, separ ate the ground of the control lines from the ground of the power lines, so that there is as little common impedance by using a bypass capacit or (etc.), so that noise is not superimposed on the v dd (no. 34) pin or the v ref (no. 40) pin. 11.9 notes on pin connections if there is more than one pin of any pin type, ensure that all the pins are connected. also, always apply the same potential to the power supply pins v dd (no. 34) pin, pv dd (no. 7) pin, and npv dd (no. 11) pin. data sheet s17102ej2v0ds 32 pd16908 12. example of application circuit i i1 + ? ? ? + i i9 out9 out1 ch1out 9 v/100 ma ch2out 8 v/100 ma battery 2.7 to 5.5 v 2.7 to 5.5 v out2 pgnd1 fb1 620 k ? 100 k ? 2200 pf 51 k ? ch1out lv dd test1 test2 agnd1 agnd2 v ref c dly c t r t c ss1 npv dd v dd 24 c ss2 28 c ss3 32 c ss4 37 c ss5 17 c ss6 21 39 38 41 40 9 10 8 34 11 53 52 43 shdnb 47 test3 48 n.c. 33 n.c. 29 n.c. 25 23 22 i i2 fb2 510 k ? 100 k ? 2200 pf 47 k ? ch2out 27 26 i i3 fb3 750 k ? 100 k ? 2200 pf 75 k ? ch3out 31 30 i i4 fb4 300 k ? 100 k ? 2200 pf 75 k ? ch4out 36 35 i i5 fb5 150 k ? 100 k ? 2200 pf 750 k ? ch5out 16 15 i i6 fb6 150 k ? 100 k ? 2200 pf 750 k ? ch6out 20 19 dcon 51 sda 45 scl 46 cs 44 50 49 18 42 0.047 f 0.047 f 0.047 f 0.1 f 0.1 f 0.1 f 22 f 11 k ? 0.047 f 0.047 f 0.047 f 150 pf + 0.1 f 22 f + pv dd 7 0.1 f 22 f + 10 f 10 h + 10 f 10 h + out3 ch3out 7.5 v/100 ma pgnd2 5 pgnd4 3 6 10 f 10 h + out5 ch5out ? 4 v/150 ma 12 10 f 10 h + out6 ch6out ? 4 v/150 ma 14 10 f 10 h + out4 ch4out 5 v/100 ma ch9out 1.5 v/1 ma pgnd3 13 4 10 f 10 h + + ? ? ? + + ? ? ? + + ? ? ? + + ? ? ? + ? + + ? ? ? + 10 f + i i8 out8 55 54 ch8out 1.8 v/1 ma ? + 10 f + i i7 out7 1 bv dd 2 56 ch7out 2.0 v/1 ma ? + 10 f + 3.3 v 220 k ? 220 k ? 240 k ? 300 k ? 180 k ? 360 k ? 3.3 v c p u v ref v ref control logic block and serial interface block soft start circuit triangular wave oscillator timer latch short-circuit protection circuit undervoltage lockout circuit reference voltage 2.0 v caution the constants shown in this figure are for reference only and do not guarantee the characteristics. set the constants and use a ppropriate components in accord ance with the actual operating conditions. data sheet s17102ej2v0ds 33 pd16908 13. package drawing item dimensions d e f hd he t 7.75 7.75 0.64 0.23 0.05 0.20 0.03 0.14 ? 0.20 0.50 0.40 0.10 0.05 0.08 0.10 0.625 0.625 0.17 0.14 ? 0.16 0.20 8.00 8.00 0.20 p56k9-50-9b4 0.03 +0.02 ?0.025 (unit:mm) a2 b b1 c c1 c2 e lp x y y1 zd ze a1 0.67 +0.08 ?0.04 a detail of p part a1 c a2 lp 0.08min. 0.08min. terminal section b1 b c1 c2 42 29 15 14 28 43 56 1 4 ? c0.5 x4 hd he e zd ze d /2 d /2 e /2 he /2 hd f s a b x4 t s a b p a s y1 s s y b e a s x bab m 56-pin plastic wqfn (8x8) notes 1 "t" and "f" excludes mold flash 2 although there are 4 terminals in the corner part of a package, these terminals are not designed for interconnection, but for manufacturing process of the package, therefor do not intend to solder these 4 terminals, solderablity of the 4 terminals are not guaranteed. data sheet s17102ej2v0ds 34 pd16908 14. recommended soldering conditions the pd168103 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than t hose recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http:// www.n ecel.com/pkg/en/mount/index.html) type of surface mount device pd16908k9-9b4-a: 56-pin plastic wqfn (8 x 8) process conditions symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours), flux: rosin flux with low chlorine (0.2 wt% or below) recommended. data sheet s17102ej2v0ds 35 pd16908 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 pd16908 the information in this document is current as of october, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 |
Price & Availability of UPD16908K9-9B4-A
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